module PE #(
    parameter DW = 8
) (
    input wire clk,
    input wire rst,
    input wire data_rst,
    input wire ini, //权重初始化阶段，控制weight的初始化，低有效
    input wire data_en,  //使能信号，低有效
    input wire  [DW-1:0]    activation_in,
    input wire  [DW-1:0]    weight_in,
    input wire  [DW*2-1:0]  pre_sum_in,
    output wire [DW-1:0]    next_weight,
    output wire [DW-1:0]    next_activation,
    output wire [DW*2-1:0]  next_sum

);

//包含3个寄存器 2个输入的寄存 一个输出的寄存
reg [DW-1:0]    activation;
reg [DW-1:0]    weight;
reg [DW*2-1:0]  pre_sum;
wire [DW*2-1:0]  mul;

//权重初始化部分
always @(posedge clk or negedge rst) begin
    if(~rst)
        weight <= 0;
    else if (~ini) begin
        weight <= weight_in;
    end
end
assign next_weight = weight;

//数据流部分
always @(posedge clk or negedge rst) begin
    if (~data_rst) begin
        activation <= 0;
    end
    else if(~data_en) begin
        activation <= activation_in;
    end
end
assign next_activation = activation;

assign mul = weight * activation;

//部分和部分
always @(posedge clk or negedge rst) begin
    if (~data_rst) begin
        pre_sum <= 0;
    end
    else if(~data_en) begin
        pre_sum <= pre_sum_in;
    end
end

assign next_sum = mul + pre_sum;

    
endmodule